--------------------------------- | FINAL CALL FOR PAPERS | --------------------------------- IEEJ 1999 ANALOG VLSI WORKSHOP ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ May 5 to 7, 1999, Grand Hotel in Taipei, TAIWAN The 1999 Analog VLSI Workshop is sponsored by The Research Committee on Electronic Circuits of The Institute of Electrical Engineers of Japan (IEEJ) and co-sponsored by IEEE Solid State Circuit Section, Taipei Chapter, Chip Implementation Center of National Science Council, National Taiwan University, National Science Council, Taiwan Ministry of Education, Electronic Research & Service Organization of Industrial Technology Research Institute, and Computer & Communicatin Research Laboratory of Industrial Technology Research Institute in cooperation with IEEE Circuits and Systems Society Tokyo Chapter. The Workshop will be held at Grand Hotel in Taipei, Taiwan on May 5 to 7, 1999 and will be preceded by three tutorial short courses on analog CAD/circuit designs on May 5. The purpose of the Workshop is the exchange of information, ideas and recent research results on analog VLSI circuits and their applications. This workshop provides an informal setting for a group of analog VLSI specialists from both industry and academia worldwide, to meet and brainstorm. The work does not have to be complete, e.g. results from a test chip are not mandatory. The topics for the Workshop include but are not limited to: Amplifiers, Filters, Comparator, Multipliers, Voltage References, Sample-And-Hold Circuits, A/D and D/A Converters, Consumer Electronics, Mixed Analog and Digital Circuits, Analog Circuit Simulators, Analog Circtui Testing, Analog Signal and Information Processing Applications (Telecommunication, Multimedia, Consumer, Medical, Automotive, Space, Military, etc.) Authors are requested to send a 200-word abstract together with information including the complete title, author name(s), affiliation(s) of author(s), and corresponding author (name, postal and e-mail addresses, telephone/fax numbers) to the following Secretariat by January 29, 1999. ^^^^^^^^^^^^^^^^ Notifications of acceptance will be sent by February 28, 1999 ^^^^^^^^^^^^^^^^^ together with Author's Kit. The official language is English. The deadline for camera-ready manuscript is March 31, 1999. ^^^^^^^^^^^^^^ It is mandatory that the accepted paper should be presented at the Workshop. Registration fees are planed to be given as follows. --------------------------------------------------- Tutorial Workshop --------------------------------------------------- Full-Time Student US$50 US$100 IEEJ or IEEE member US$100 US$250 Non-IEEJ and Non-IEEE member US$120 US$300 --------------------------------------------------- Further information can be obtained from the Secretariat by e-mail or FAX, or visiting the Workshop Web site given as below. Secretariat Prof. Akira Hyogo Department of Electrical Engineering, Science University of Tokyo 2641 Yamazaki, Noda-shi, Chiba, 278-8510, Japan E-Mail: hyogo@ee.noda.sut.ac.jp FAX: +81-471-22-5171 Workshop Web site URL: http://ieej.si.noda.sut.ac.jp/AVLSIWS/