Advance Program (Ver.5.00 98/5/27) IEEJ (The Institute of Electrical Engineers of Japan) The 2nd International Analog VLSI Workshop June 5,6 1998 DAYS INN, Santa Clara, California, USA Cooperation: IEEE Circuits and Systems Society Tokyo Chapter Time Table of the 2nd Analog VLSI Workshop Sessions June 5(Fri.) 6(Sat.) _________________________________________________________________________ AM 9:00 FR-1 9:00 SA-1 | 4 papers | 4 papers 10:20 10:20 10:40 FR-2 10:40 SA-2 | 4 papers | 4 papers 12:00 12:00 _________________________________________________________________________ PM 13:30 FR-3 13:30 SA-3 | Special Talk 1 | 5 papers 14:40 | 15:00 FR-4 15:10 | 4 papers 15:30 SA-4 16:20 | 16:30 FR-5 | 6 papers | Special Talk 2 | 17:40 17:30 18:00 Banquet at DAYS INN _________________________________________________________________________ June, 5th, Friday (AM) __FR-1 ( 9:00-10:20)_____________________________________________________ ECT-98-30 1) Compensation Techniques for Operational Transresistance Amplifier Based Filters Robert A. Brannen, Hassan O.Elwan and Mohammed Ismail (The Ohio State University, U.S.A.) ECT-98-31 2) Integrator-Based Filter Structures with Good Frequency Characteristics Kazuyuki Wada, Shigetaka Takagi and Nobuo Fujii (Tokyo Institute of Technology, Japan) ECT-98-32 3) On the Potential Instability of an RC Active Filter with Op-amps Tetsuo Nishi and Masato Ogata (Kyushu University, Japan) ECT-98-33 4) A Continuous Time Normalized LMS Adaptive Filter Structure Luis Nino-de-Rivera and Hector Perez-Meana (SEPI ESIME Culhuacan National Polytechnic Institute, Mexico) and Edgar Sanchez-Sinencio (Texas A&M University, U.S.A.) __FR-2 (10:40-12:00)_____________________________________________________ ECT-98-37 5) A Wireless Data System Constructed of SAW-Devices and Its Applications to Medical Cares Kenji Matsumura (Osaka University, Japan, & KCS Co., Ltd., Japan), Gen Fujita and Isao Shirakawa (Osaka University, Japan), Hiroshi Inada (National Cardiovascular Center Research Institute, Japan) ECT-98-35 6) Near Optimum Analog Integrator Circuit Juan Carlos Sanchez-Garcia, Luis Nino-de-Rivera and Hector Perez-Meana (SEPI ESIME Culhuacan National Polytechnic Institute, Mexico) ECT-98-36 7) The Desing of 400MHz Bandpass Amplifier Using Low-Cost CMOS Technology Chung-Yu Wu, Pei-Feng Wu, Guo-Chi Lin, Hsun-Hsiu Huang and Din-Hao Hsiao (National Chiao Tung University, Taiwan) ECT-98-34 8) A Differential Attenuator for Phase Compensation System of Feedback Integrators Fujihiko Matsumoto and Yasuaki Noguchi (National Defense Academy, Japan) (PM) __FR-3 (13:30-14:40)_____________________________________________________ ECT-98-43 9) [Special Talk 1] Why Spice is still center of analog CAD tools Takahide Inoue (Sony Electronics Inc, U.S.A.) and Ian Getreu (Analogy, U.S.A) __FR-4 (15:00-16:20)_____________________________________________________ ECT-98-38 10) Novel Low Power and Constant gm Rail-to-Rail Operational Amplifier using Multiple Input Floating Gate Transistors Seung C. Choi and Allan Lin (Xicor, Inc., U.S.A.) and J. Ramirez-Angulo (New Mexico State University, U.S.A.) ECT-98-39 11) A Design Technique of the CMOS Circuit with a Very Low Impedance Terminal for Stability Eitake Ibaragi, Akira Hyogo and Keitaro Sekine (Science University of Tokyo, Japan) ECT-98-40 12) Low Voltage Low Power Class AB OTA and V-I Converter Hassan O.Elwan (The Ohio State University, U.S.A.), Changku Hwang (Hitachi Ltd., Japan) Mohammed Ismail (The Ohio State University, U.S.A.), Akira Hyogo (Science University of Tokyo, Japan) ECT-98-41 13) A CMOS Four-Quadrant Analog Multiplier for Low-Voltage Low-Power Hyun-Seung Choi, Nam-Gyun Kim and Dong-Yong Kim (Chonbuk National University, Korea) __FR-5 (16:30-17:40)_____________________________________________________ ECT-98-42 14) [Special Talk 2] The Education and Research of Analog VLSI in Taiwan Chung-Yu Wu (National Chiao Tung University, Taiwan) _________________________________________________________________________ June, 6th, Saturday (AM) __SA-1 ( 9:00-10:20)_____________________________________________________ ECT-98-44 15) On the Extraction of Spice Level-3 MOS Transistor Parameters Tuna B.Tarim (Istanbul Technical University, Turkey & The Ohio state University, U.S.A.), Metin Yazgi and H.Hakan Kuntman (Istanbul Technical University, Turkey) ECT-98-45 16) A Graphical Model of the MOS Differential Pair Roelof F.Wassenaar (University of Twente, The Netherlands) ECT-98-46 17) Statistical Design of a Low Voltage Low Power Square-Law CMOS Cell Tuna B.Tarim (Istanbul Technical University, Turkey & The Ohio state University, U.S.A.) H.Hakan Kuntman (Istanbul Technical University, Turkey) and Mohammed Ismail (The Ohio state University, U.S.A.) ECT-98-47 18) The Asymptotic Periodic Waveform Evaluation Method for Steady State Analysis Sermsak Uatrongjit (Chiang Mai University, Thailand) and Nobuo Fujii (Tokyo Institute of Technology, Japan) __SA-2 (10:40-12:00)_____________________________________________________ ECT-98-48 19) A 4GHz Multiple Modulus Prescaler in CMOS Rami Ahola and Kari Halonen (Helsinki University of Technology, Finland) ECT-98-49 20) Phase Detectors/Phase Frequency Detectors for High Performance PLLs Hiroyasu Yoshizawa, Kenji Taniguchi and Kenichi Nakashi (Kyushu University, Japan) ECT-98-50 21) Speedup of Frequency Switching Time in PLL Frequency Synthesizers Using Target Frequency Detector Shigeki Obote (Tottori University, Japan), Yasuaki Sumi (Tottori SANYO Electric Co., Ltd., Japan) Naoki Kitai, Kouichi Syoubu, Yutaka Fukui and Yoshio Itoh (Tottori University, Japan) ECT-98-51 22) A Multi-Loop PLL Frequency Synthesizer Yasuaki Sumi (Tottori SANYO Electric Co., Ltd., Japan), Kouichi Syoubu, Shigeki Obote, Yutaka Fukui and Yoshio Itoh (Tottori University, Japan) (PM) __SA-3 (13:30-15:10)_____________________________________________________ ECT-98-52 23) Combined Hartley Image-Reject Receiver with Bandpass Delta-Sigma Modulator Tsung-Yuan Chang and Steven B. Bibyk (The Ohio State University, U.S.A.) ECT-98-53 24) Nonlinear Quantization in Low Oversampling Ratio Sigma-Delta Noise Shapers for RF Applications A. Gothenberg and H. Tenhunen (Royal Institute of Technology, Sweden) ECT-98-54 25) A Reduced Delay Method for Improving the Performance of Sigma-Delta Analog-to-Digital Converters (ADC) Louis Luh, John Choma, Jr and Jeffrey Draper (University of Southern California, U.S.A.) ECT-98-55 26) Switch Arrayed CMOS ADC for Low Power Applications Joung Chul Ahn (Electronics and Telecommunications Research Institute, Korea) Ju Ho Shon and Dong Yong Kim (Chonbuk National University, Korea) ECT-98-56 27) A Low Power Transistor-Only CMOS Current-Mode A/D Converter Architecture Nasirul Chowdhury, Hassan O.Elwan and Mohammed Ismail (The Ohio State University, U.S.A.) __SA-4 (15:30-17:30)_____________________________________________________ ECT-98-57 28) Low-Power Bipolar Sample-and-Hold Amplifiers Masakatsu Kobayashi, Akira Hyogo and Keitaro Sekine (Science University of Tokyo, Japan) ECT-98-58 29) Differential Analog Data Path Offset Calibration Method Takeo Yasuda (IBM Japan Ltd., Japan) and Hajime Andoh (Silicon Systems Inc., Japan) ECT-98-59 30) Regulated-High-Swing Cascoding and Its Applications Esa Tiiliharju (Helsinki University of Technology, Finland), Mohammed Ismail (The Ohio State University, U.S.A.) and Kari Halonen (Helsinki University of Technology, Finland) ECT-98-60 31) An Analog CMOS IC for Template Matching A. Ahmed Biyabani, L. Richard Carley and Takeo Kanade (Carnegie Mellon University, U.S.A.) ECT-98-61 32) Pulse-Type Hardware Neuron Model for Future IC Design Based on the Modified BVP Equations Katsutoshi Saeki, Yoshifumi Sekine (Nihon University, Japan) and Kazuyuki Aihara (The University of Tokyo and Japan Science and Technology Co., Japan) ECT-98-62 33) A Systhesis of A High Transformer Ratio SC DC-DC Converter Operated by Two-Phases Clock and Its Analysis Koji Tateno, Akira Hyogo, and Keitaro Sekine (Science University of Tokyo, Japan) _________________________________________________________________________ Organizing Committee Committee Chair Nobuo Fujii (Tokyo Inst. of Tech.) Committee Secretaries Masayuki Ishikawa (Kisarazu National College of Tech.) Hiroshi Tanimoto (Toshiba Corp.) Futao Yamaguchi (Sony Corp.) Committee Co-Secretary Akira Hyogo (Science Univ. of Tokyo) Committee Members Takahiro Inoue (Kumamoto Univ.) Mitsuo Okine (Hiroshima Inst. of Tech.) Yuichi Ono (Electrotechnical Laboratory) Kazuo Kato (Hitachi Ltd.) Noriyoshi Kambayashi (Nagaoka Univ. of Tech.) Kazuyuki Saijyo (Sony Corp.) Noboru Shibuya (Takusyoku Univ.) Yasuhiro Sugimoto (Chuo Univ.) Keitaro Sekine (Science Univ. of Tokyo) Yoshifumi Sekine (Nihon Univ.) Shigetaka Takagi (Tokyo Inst. of Tech.) Toshiyuki Tahara (OKI Electric Industory Co. Ltd) Tuneo Tsukahara (NTT) Yutaka Fukui (Tottori Univ.) Masataka Mitani (Matsushita Electric Works, Ltd.) Seijiro Moriyama (Toshiba Corp.) Masaki Yamakawa (Mitsubishi Electric Corp.) Masatsune Yamaguchi (Chiba Univ.) Hiromichi Watanabe (Niigata Univ.) Local Arrangement Chair Jin-Qin Lu (NEC Electronics Inc.) Advisory Committee Members Sergio Bampi (Federal University at Porto Alegre, Brazil) Mohammed Ismail (The Ohio State University, USA) Tor Sverre Lande (University of Oslo, Norway) Franco Maloberti (University of Pavia, Italy) Minoru Nagata (Hitachi Ltd., Japan) Veikko Porra (Helsinki University of Technology, Finland) Bing J. Sheu (University of Southern California, USA) Ahmed M Soliman (Cairo University, Egypt) Chris Toumazou (Imperial College of Science, Technology and Medicine, UK) Chung-Yu Wu (National Chiao-Tung University, ROC) Takeshi Yanagisawa (Shibaura Institute of Technology, Japan) _________________________________________________________________________