****************************************************************************** 1999 International Analog VLSI Workshop ADVANCE PROGRAM (Ver. 1) ****************************************************************************** Web Site: http://www.cic.edu.tw/avlsiws99/ (Web Site: http://ieej.si.noda.sut.ac.jp/AVLSIWS/) IEEJ (The Institute of Electrical Engineers of Japan) The 3rd International Analog VLSI Workshop Co-sponsors : IEEE Solid-State Circuit Society Taipei Chapter Chip Implementation Center of National Science Council, R.O.C. National Taiwan University National Science Council, R.O.C. Ministry of Education, R.O.C. Electronics Research & Service Organization of Industrial Technology Research Institute, R.O.C. Computer & Communicatin Research Laboratories of Industrial Technology Research Institute, R.O.C. IEEE Taipei Section Co-operation: IEEE Circuits and Systems Society Tokyo Chapter Timetable of Workshop Sessions May 5(Wed.) May 6(Thu.) May 7(Fri.) ________________________________________________________________________________ AM 8:30 8:30 | Opening Remark | 8:40 | | S1:Keynote Speech | 9:30 | S6: 6 papers | Break | 9:45 | 10:00 | | | | 10:30 | Tutorial 1 | S2: 7 papers | Break | | 10:45 11:30 | | S7: 4 papers | | | | Lunch 12:05 12:05 | | Lunch | Lunch 13:00 13:00 13:00 ________________________________________________________________________________ PM 13:00 13:00 13:00 | | S3:Invited Speech | | Tutorial 2 13:50 | | | Break | | 14:05 | S8: 7 papers 14:30 | | | Break | | 15:00 | | | | S4: 7 papers 15:20 | | | Break | Tutorial 3 | 15:35 | | | | 16:25 | S9: 6 papers 16:30 | Break | 16:40 | | S5: 4 papers 17:35 18:00 | Banquet | ________________________________________________________________________________ (20min.(with Q&A) / regular paper) May 5, Wednesday __Tutorial (10:00-16:30)_____________________________________________________ T1) CAD Tools for Analog and Mixed-Signal IC Design Georges Gielen (Katholieke Universiteit Leuven, Belgium) T2) Analog RF Circuit Techniques for Wireless Applications Satoshi Tanaka (Hitachi Ltd., Japan) T3) Design Techniques for Integrated Low-Voltage Continuous-Time Filter Hiroshi Tanimoto and Tetsuro Itakura (Toshiba Corp., Japan) ___________________________________________________________________________ May 6, Thursday (AM) __Opening Remark ( 8:30-8:40)______________________________________________ __S1 ( 8:40-9:30)_________________________________________________ S1.1) [Keynote Speech] Perspectives of Taiwan IC Industry Jyuo-Min Shyu (Electronics Research & Service Organization of Industrial Technology Research Institute, Taiwan) __S2 ( 9:45-12:05)_________________________________________________ S2.1) A 10-Bit Fast Pipelined ADC using Current-Mode Techniques Chen-Hao Chang, and Chun-Teng Huang (National Chung-Hsing University, Taiwan) S2.2) Analysis and Comparison of High-Order Cascaded Continuous-Time Sigma Delta Modulator Chi-Hung Lin , and Mohammed Ismail (The Ohio State University, U.S.A.) S2.3) A Chip Design and Implementation of A 13-bit High-Order Oversampling Modulator for ISDN-U Interface Sau-Mou Wu, Rou-Yi Liu, and Yu-Chin Chu (Yuan-Ze University, Taiwan) S2.4) Integrator Non-Ideality Analysis of Low Oversampling Ratio Sigma Delta Noise Shapers for Wideband Radio Applications Andreas Gothenberg, and Hannu Tenhunen (Royal Institute of Technology, Sweden) S2.5) A Novel Delta-Sigma Time-to-Digital Converter Using Delay Line Hsi-Yuan Wang (National Chiao-Tung University, Winbond Electronics Corp,Taiwan), and Jieh-Tsorng Wu (National Chiao-Tung University,Taiwan) S2.6) Design and Analysis of an Oversampling D/A Converter in DMT-ADSL Systems Yonghong Gao(Royal Institute of Technology, Sweden), J Jacob Wikner (Linkoping University, Sweden), and Hannu Tenhunen (Royal Institute of Technology, Sweden) S2.7) A Small Coefficient Spread Structure for High-Q Bandpass Sigma-Delta Modulator Design Shuenn-Yuh Lee, Jiann-Jong Wang, Yong-Tee Teo, Tai-Haur Kuo (National Cheng Kung University,Taiwan), and Jaw-Juinn Horng (Industrial Technology Research Institute Computer & Communication Research Laboratories, Taiwan) (PM) __S3 (13:00-13:50)_________________________________________________ S3.1) [Invited Speech] Systematics Design of Analog Macrocells Georges Gielen (Katholieke Universiteit Leuven, Belgium) __S4 (14:05-16:25)__________________________________________________ S4.1) A New Prescaler PLL Frequency Synthesizer with Multi-Programmable Divider Yasuaki Sumi (Tottori SANYO Electric Co. Ltd, Japan), Shigeki Obote, Naoki Kitai, Ryousuke Furuhashi, Hidekazu Ishii, Yoshio Itoh, and Yutaka Fukui(Tottori University, Japan) S4.2) A 1 V CMOS Dynamic Back-Gate Forward Bias Prescaler for Frequency Synthesizer Application June-Ming Hsu, Shen-Iuan Liu, Ching-Yuan Yang, and Guang-Kaai Dehng (National Taiwan University, Taiwan) S4.3) Prescaler PLL Frequency Synthesizer Introducing Multi-(N+1/2) Programmable Dividers Yasuaki Sumi (Tottori SANYO Electric Co. Ltd, Japan), Shigeki Obote, Naoki Kitai, Hidekazu Ishii, Ryousuke Furuhashi, Yoshio Itoh, and Yutaka Fukui (Tottori University, Japan) S4.4) A 750MHz/1-V 128/129 Prescaler Using a Voltage Doubler Guang-Kaai Dehng, and Shen-Iuan Liu (National Taiwan University, Taiwan) S4.5) Improved Integer-N Frequency Synthesizer with Higher Input Frequency than Channel Spacing Joung-Chul Ahn (Electronics and Telecommunications Research Institute, Korea), Sun-Hong Kim, Seok-Woo Choi, and Dong-Yong Kim (Chonbuk National University, Korea) S4.6) A Programmable Delay Element for Low-Power PLL Applications Kuo-Hsing Cheng (Tamkang University, Taiwan) S4.7) A Proposal for a Non-Pseudo-Locked FLL Mitsutoshi Yahara (Tokai University Fukuoka Junior College, Japan), Hirofimi Sasaki, and Kuniaki Fujimoto (Kyushu Tokai University, Japan) __S5 (16:40-18:00)__________________________________________________ S5.1) A Novel CMOS Analog Square Circuit Free from Mobility Reduction and Body Effect Eitake Ibaragi, Akira Hyogo, and Keitaro Sekine (Science University of Tokyo, Japan) S5.2) 1.5V New GHz CMOS Analogue Squarer and Four-Quadrant Multiplier for RF Signal Processing Simon Cimin Li (National Yunlin University of Science and Technology, Taiwan) S5.3) Single/Dual Power Supply Differential Input Voltage Four-Quadrant Analog Multiplier Using Quarter-Square Technique Ittipong Chaisayun, Kobchai Dejhan, Fusak Cheevasuvit (King Mongkut's Institute of Technology Ladkrabang, Thailand), and Chatcharin Soonyeekan (Kasem Bundit University, Thailand) S5.4) A Noise Modeling Approach For LPTV System and Its Application to RF CMOS Mixer Li Li, Jianhua Guo, and Hannu Tenhunen (Royal Institute of Technology, Sweden) ___________________________________________________________________________ May 7, Friday (AM) __S6 ( 8:30-10:30)__________________________________________________ S6.1) A 0.5um Operational Transconductance Amplifier-Capacitor Filter with Concurrent Error Detection Capability Kuen-Jong Lee, and Wei-Chiang Wang (National Cheng Kung University, Taiwan) S6.2) A 2V 3rd-Order Fully-Differential CMOS Gm-C Filter Chi-Hung Lin, Mohammed Ismail, and Chunlei Shi (The Ohio State University, U.S.A.) S6.3) Realization of a precise voltage divider with high input resistance for a triple-tail cell in a gyrator-C filter Fujihiko Matsumoto, and Yasuaki Noguchi (National Defense Academy, Japan) S6.4) Design Techniques for Low-Voltage VHF BiCMOS Continuous-Time Filters with Automatic Tuning Tsung-Sum Lee (National Yunlin University of Science and Technology, Taiwan) S6.5) Variable Current Gain Log Domain Filter and Its Application to CCII Sumitaka Ohtake, Akira Hyogo, and Keitaro Sekine (Science University of Tokyo, Japan) S6.6) A 1.2 V Rail-to-Rail Analog CMOS Rank Filter Yu-Cherng Hung, and Bin-Da Liu (National Cheng Kung University, Taiwan) __S7 (10:45-12:05)__________________________________________________ S7.1) A 622Mbps CMOS Transimpedance Amplifier for SONET/SDH and ATM LAN Optical Receiver Chung-Chiang Ku, Ming-Hong Tsai, Choa-Hui Lin, and Kuang-Chung Tao (Industrial Technology Research Institute, Taiwan) S7.2) A CMOS RF Power Amplifier Low Voltage Design Technique Jianhua Guo, Mohammed Ismail, and Hakan Olsson (Royal Institute of Technology, Sweden) S7.3) A 2.4GHz CMOS Low-IF Receiver Yi Lu, Kuang-Hu Huang, Po-Chiun Huang, and Chorng-kuang Wang (National Taiwan University, Taiwan) S7.4) High Speed ECL to CMOS Interface and Output Buffer combining Bipolar with CMOS Masayuki Katakura, and Genichiro Oga (SONY Corporation, Japan) (PM) __S8 (13:00-15:20)__________________________________________________ S8.1) Parallel IIR Analog Filter Structure Using The Discrete Cosine Transform Mariko Nakano-Miyatake, Hector Perez-Meana, Luis Nino-de-Rivera, and Juan Carlos Sanchez-Garcia (SEPI ESIME Culhuacan National Polytechnic Institute, Mexico) S8.2) A New Current-Mode Universal Biquad Filter Using Only One Current-Feedback Amplifier Ro-Min Weng, Liang-Gee Chen, and Maw-Huei Lee (National Taiwan University, Taiwan) S8.3) Design of 1.2V CMOS Low-Frequency Current-Mode Filter Dong-Yong Kim (Chonbuk National University, Korea), Joung-Chul Ahn (Electronics and Telecommunications Research Institute, Korea), Jong-Hyun Park, and Seok-Woo Choi (Chonbuk National University, Korea) S8.4) A Design of a Low-Voltage Current-Mode Fully-Differential Analog CMOS Integrator Using FG-MOSFETs and Its Implementation Takahiro Inoue, Hideo Nakane, Yuuji Fukuju (Kumamoto University, Japan), and Edgar Sanchez-Sinencio (Texas A&M University, U.S.A.) S8.5) A CMOS Voltage-Controlled Grounded Resistor Circuit Pipat Prommee, Kobchai Dejhan, Fusak Cheevasuvit (King Mongkut's Institute of Technology Ladkrabang, Thailand), and Chatcharin Soonyeekan (Kasem Bundit University, Thailand) S8.6) A Clock-feedthrough Compensation Technique for Switched-Current Circuits Shu-Chuan Huang (Tatung Institute of Technology, Taiwan) S8.7) GaAs MESFET High Output Impedance Current Mirror Nobukazu Takai, and Nobuo Fujii (Tokyo Institute of Technology,Japan) __S9 (15:35-17:35)__________________________________________________ S9.1) A 6.25~100 MHz CMOS Clock Generator For Video Line-Locked Chang-Ho Liou (National Taiwan Ocean University, Taiwan), Gene Chuang (Trumpion Microelectronics Inc,Taiwan), and Wan-Rone Liou (National Taiwan Ocean University, Taiwan) S9.2) Low Cost Frequency Doubler Circuit Using Duty Cycle Control Buffer Hwang-Cherng Chow (Industrial Technology Research Institute, Taiwan) S9.3) Design of a Low Power Analog Defuzzifier Robert. H. Fujii, and Eishin Hoshi (University of Aizu, Japan) S9.4) An Analog Motion Field Detection Chip Based on Optical Flow Computation Ming-Han Lei, and Tzi-Dar Chiueh (National Taiwan University, Taiwan) S9.5) ESD Protection Design for Analog Pins with a Very Low Input Capacitance Ming-Dou Ker (Industrial Technology Research Institute, Taiwan), and Hun-Hsien Chang (Taiwan Semiconductor Manufacturing Company, Taiwan) S9.6) A New Electronic Circuit Breaker using 0.6um CMOS Technology Ming-Hsiang Chiou, Yau-Jang Liu, and Klaus Y. J. Hsu (National Tsing Hua University, Taiwan) ------------------------------------------------------------------------------ ------------------------------------------------------------------------------ 1999 International Analog VLSI Workshop ORGANIZING COMMITTEE ************************************************** General Chair: Nobuo Fujii (Tokyo Inst. of Tech.) General Co-Chair: Chorng-Kuang Wang (National Taiwan Univ.) Technical Program Chair: Jen-Sheng Hwang (Chip Impelementation Center) Technical Program Co-Chair: Keitaro Sekine (Sceince Univ. of Tokyo) Technical Program Committee Secretaries: Meng-Lieh Sheu (Chip Impelementation Center) Masayuki Ishikawa (Kisarazu National College of Tech.) Hiroshi Tanimoto (Toshiba Corp.) Futao Yamaguchi (Sony Corp.) Committee Co-Secretaries: Akira Hyogo (Science Univ. of Tokyo) Technical Profgram Committee Members: Chen-Hao Chang (National Chung Hsing Univ.) Kuo-Hsing Cheng (Tam Kang Univ.) Chin-Fong Chiu (Chip Implementation Center) Tzi-Dar Chiueh (National Taiwan Univ.) Yutaka Fukui (Tottori Univ.) Takahiro Inoue (Kumamoto Univ.) Noriyoshi Kambayashi (Nagaoka Univ. of Tech.) Kazuo Kato (Hitachi Ltd.) Tai-Haur Kuo (National Cheng Kung Univ.) Ping-Hsing Lu (Industrial Technology Research Institute) Masataka Mitani (Matsushita Electric Corp.) Seijiro Moriyama (Toshiba Corp.) Mitsuo Okine (Hiroshima Inst. of Tech.) Kazuyuki Saijyo (Sony Corp.) Yoshifumi Sekine (Nihon Univ.) Noboru Shibuya (Takushoku Univ.) Ming-Tang Shih (Winbond Electronics Corp.) Yasuhiro Sugimoto (Chuo Univ.) Toshiyuki Tahara (OKI Electric Industry Co. Ltd.) Shigetaka Takagi (Tokyo Inst. of Tech.) Tsuneo Tsukahara (NTT) Jinn-Shyan Wang (National Chung Cheng Univ.) Hiromichi Watanabe (Niigata Univ.) Cheng-Wen Wu (National Tsing Hua Univ.) Jieh-Tsorng Wu (National Chiao Tung Univ.) Jiin-Chuan Wu (National Chiao Tung Univ.) Tain-Shun Wu (Industrial Technology Research Institute) Masatsune Yamaguchi (Chiba Univ.) Masaki Yamakawa (Mitsubishi Electric Corp.) Advisory Committee Members: Sergio Bampi (Federal Univ. at Porto Alegre, Brazil) Mohammed Ismail (The Ohio State Univ. USA) Tor Sverre Lande (Univ. of Oslo, Norway) Franco Maloberti (Univ. of Pavia, Italy) Minoru Nagata (Hitachi Ltd., Japan) Veikko Porra (Helsinki Univ. of Tech., Finland) Bing J. Sheu (Univ. of Southern California, USA) Ahmed M. Soliman (Cairo Univ. Egypt) Chris Toumazou (Imperial College of Science, UK) Chung-Yu Wu (National Chiao-Tung Univ., Taiwan) Takeshi Yanagisawa (Shibaura Inst. of Tech., Japan) ********************************************************************************